The present invention relates to semiconductor structures containing poly/silicide stacks.
Gates and interconnects of semiconductor structures may be conveniently made from doped polycrystalline silicon (poly). However, as the size of these structures continues to decrease, the resistivity of the poly becomes significant. Including a more conductive material, atop the poly, such as a metal silicide, mitigates this problem. These multilayer structures are often referred to as stacks.
During patterning of the stacks, it is desirable to restore the quality of the thin oxide layer near the foot of the stack and round the corner. In the case of a gate, this oxide is often referred to as the gate oxide. When the gate is made of only poly, a thin thermally grown oxide, on the sides of the gate, serves this purpose. In the case of a stack, simple thermal oxidation can lead to abnormal oxidation and defects that may interfere with subsequent processing of the semiconductor structure, such as “glob” formation at the poly/silicide interface (see, for example, “Improved Thermal Stability of CVD WSix During Furnace Oxidation by a Rapid Thermal Anneal Pretreatment”, Blosse, Alain P., Presentation to MRS conference, 1998; and “Sidewall oxidation behavior of dichlorosilane-based W-polycide gate”, Kim, Hyeon-Soo et al., J. Vac. Sci. Technol. B 19(2), Mar/April 2001).
FIGS. 1 and 2 illustrate steps used in forming a poly/tungsten silicide gate stack. On a silicon substrate 2 having a thin oxide or oxynitride layer 10, is formed a poly layer 4 with or without a tungsten nitride barrier, then a tungsten silicide layer 6 and a silicon nitride capping layer 8; these layers are patterned to form a gate, as illustrated in FIG. 1. This structure is typically then subjected to rapid thermal annealing (RTA) at 800° C. for 30 seconds in a nitrogen or argon atmosphere (converting the phase structure of the tungsten silicide to a tetragonal phase, and transforming the barrier layer of tungsten nitride, if present, into tungsten silicide nitride), followed by oxidation (wet or dry) at 850–900° C. for about 30 minutes to 1 hour, to form sidewall oxide 12, as shown in FIG. 2.
Further processing allows for making semiconductor devices: doping of the substrate using the gate stack as a mask may be used to form lightly doped regions; applying an insulating layer, followed by etching, may be used to form spacers on the gate stack; heavy doping of the substrate using the gate stack and spacers as a mask may then be used to form source/drain regions; and further formation of oxide layers, vias, contacts and metallization, may be used to complete device formation. These types of processes are described in, for example, U.S. Pat. No. 5,756,392.
The process outlined in FIGS. 1 and 2 produces sidewall oxide that is at least two times thicker, adjacent the tungsten silicide, than adjacent the poly, causing an irregular gate profile. Shadowing during subsequent implantations, and altered spacer shape, both resulting from this irregular gate profile, can lead to degraded transistors formed from this semiconductor structure.